1. Field of the Invention
The present invention relates to a clock switching circuit, particularly to a clock switching circuit, which can switch multiple dynamic clocks.
2. Description of the Related Art
In IC design, when a system cannot manage clock switching well but has to switch between two clocks separately with different phases and speeds, the system may have the problem of clock glitch or timing insufficiency.
A clock glitch and a timing insufficiency of an output clock signal clk_out are respectively shown in FIG. 1A and FIG. 1B. In FIG. 1A and FIG. 1B, the switch signal is used to determine whether the output clock signal clk_out is clock signal 1 (clk 1) or clock signal 2 (clk 2). However, during a clock switching operation of either from clk 1 to clk 2 or from clk 2 to clk 1, the clock glitch shown in FIG. 1A or the timing insufficiency shown in FIG. 1B may occur. Therefore, a clock switching circuit, which can avoid the abovementioned problems, is necessary. The U.S. patent of Publication No.2004/0095166A1 “Clock Switching Circuit” proposes a clock switching circuit to prevent the abovementioned problems. The circuit of the conventional technology needs an extra select signal generator to control signals; however it causes some inconveniences in usage.
Accordingly, the present invention proposes a clock switching circuit to overcome the abovementioned problems and simplify the operation of switching clock signals.